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SY89538L
3.3V Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay
General Description
The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for enterprise switch, router, and multiprocessor server applications. This family is ideal for generating internal system timing requirements up to 750MHz for multiple ASICs, FPGAs, and NPUs. These devices integrate the following blocks into a single monolithic IC: * * * * * * * PLL (Phase-Lock-Loop) based synthesizer Zero-delay MUX and feedback capability 1:4 LVPECL fanout 1:3 LVDS fanout Clock generator (dividers) Logic translation (LVPECL, LVDS)
Precision Edge(R)
Features
* Integrated programmable synthesizer with multiple output dividers, fanout buffers, and clock drivers * Zero-delay capability: 29.375MHz to 756MHz * Reference clock input: 9.325MHz to 756MHz * Input MUX accepts a reference and a crystal (XTAL) source - Ideal for reference backup clock source or system test frequency source - Patent-pending unique input MUX isolates XTAL and reference inputs which minimizes crosstalk * Guaranteed AC performance: - Output frequency range: 29.375MHz to 756MHz - <150psPP total jitter - <6psRMS cycle-to-cycle jitter (XTAL Input) - <8psPP deterministic jitter - <0.7psRMS crosstalk induced jitter - <75ps output-to-output skew * TTL/CMOS-compatible control logic * Five-independently programmable output frequency banks: - Four differential LVPECL output banks - One differential LVDS output bank with three output pairs * Output bank synchronization control pin * Output enable * 3.3V 10% power supply (2.5V output capable) * Guaranteed over the industrial temperature range (-40C to +85C) * Available in a 64-pin EPAD-TQFP
Five-independently programmable output banks This level of integration minimizes additive jitter and part-to-part skew associated with discrete alternatives, resulting in superior system-level timing with reduced board space and power. For applications that do not require a zero-delay function, see the SY89537L. All support documentation can be found on Micrel's web site at: www.micrel.com.
Applications
* Enterprise routers, switches, servers and workstations * Parallel processor-based systems * Internal system clock generation for ASICs, NPUs and FPGAs
Markets
* LAN/WAN * Enterprise servers * Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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SY89538L
Typical Application
Functional Block Diagram
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Ordering Information(1)
Part Number SY89538LHG SY89538LHGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type H64-1 H64-1
Operating Range Industrial Industrial
Package Marking SY89538LHG with Pb-Free bar-line indicator SY89538LHG with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
64-Pin EPAD TQFP (H64-1)
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Pin Description
Power
Pin Number 1 6, 56 Pin Name VCCA VCCD Pin Function Analog PLL Power Pin. Connects to "quiet" 3.3V supply. 3.3V power pins must be connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitors and place them as close to the VCCA pin as possible. Digital Logic Core Power Pin. VCCD connects to a 3.3V supply. All power pins must be connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitors and place them as close to the VCCD pin as possible. LVDS and LVPECL Output Driver Power Pins. These outputs can be powered from a 2.5V or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V 10% or 2.5V 5%. All power pins must be connected together on the PCB. Bypass with 0.1F//0.01F low ESR capacitor and place them as close to the VCCO pin as possible. Analog PLL Ground. Connect to "quiet" ground. GNDA and GND must be connected together on the PCB. Ground: GND pins and exposed pad must both be connected to the same ground plane.
19, 40, 43, 51
VCCO
15 16, 30, 31, 47, 55
GNDA GND, Exposed Pad
Control and Configuration
Pin Number 62 Pin Name LR Pin Function Analog Input/Output. Provides the reference voltage for the PLL loop filter and is used with the LF pin. See "External Loop Filter Considerations" for recommended loop filter values. Analog Input/Output. Provides the loop filter node for the PLL. See "External Loop Filter Considerations" for recommended loop filter values. TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inputs. The two-bit input pre-scalar divides the input reference frequency by /1, /2, /4, or /8. RSEL0 is the LSB bit. See "Reference Input Divider and Zero Delay MUX Divider Select Table" for proper decoding. The threshold voltage VTH = VCC/2. Internal 25k pull-up. The default logic is HIGH. TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input. Internal 25k pull-up. The default is logic HIGH, and selects the XTAL input. The threshold voltage VTH = VCC/2. Logic HIGH: XTAL Select Logic LOW: Reference Input Select TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL, DSEL, and LEN are used together to decode the selection and post divider of the LVDS outputs. Internal 25k pull-up. See "LVDS Output Post-Divider and Frequency Select Table" for proper decoding. The threshold voltage VTH = VCC/2. The default logic is HIGH. TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and acts as a frequency select pin. LEN, DSEL, and LSEL are used together to decode the selection and post divide of the LVDS output bank, see the "LVDS Output PostDivider and Frequency Select Table" for proper decoding. Internal 25k pull-up. When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are HIGH. The threshold voltage VTH = VCC/2. The default logic is HIGH. TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx, DSEL and PENx are used together to decode the selection and post divider of the PECL outputs. PSELx pins include an internal 25k pull-up. The threshold voltage VTH = VCC/2. See "LVPECL Output Post-Divider and Frequency Select Table" for proper decoding.
63 2, 7
LF RSEL1, RSEL0
10
INSEL
36
LSEL
37
LEN
23 25 57 59
PSEL0 PSEL1 PSEL2 PSEL3
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Pin Description
Control and Configuration (continued)
Pin Number 24 26 58 60 46 Pin Name PEN0 PEN1 PEN2 PEN3 SYNC Pin Function TTL/CMOS input enable pin. Used to control the PECL POUT0-POUT3 outputs and as a frequency select pins. PENx, PSELx, and DSEL are used together; see the "LVPECL Output Post-Divider and Frequency Select Table" for proper decoding. PENx contains internal 25k pull-up. When disabled, PECL0-PECL3 outputs are a logic LOW. The threshold voltage VTH = VCC/2. TTL/CMOS Output Bank Synchronization Control. Internal 25k pull-down. The default state is HIGH. After any bank has been programmed, all PECL and LVDS outputs are synchronized when the SYNC control pin is toggled with a HIGH-LOWHIGH transition. See "Synchronization" section for details. The threshold voltage VTH = VCC/2. TTL/CMOS Input Select Control. Selects either internal or external feedback (zero-delay function). Internal 25k pull-up. The threshold voltage VTH = VCC/2. Default is logic HIGH, and selects internal feedback. Logic HIGH: Internal feedback (from the Programmable Divider) Logic Low: External feedback (from the FBIN inputs) TTL/CMOS Programmable Divider-Select Control. Internal 25k pull-down. Default is logic LOW. The threshold voltage VTH = VCC/2. See "Programmable-Divider Select Table" for proper decoding. TTL/CMOS Programmable Divider-Select Control. Internal 25k pull-up. Default is logic HIGH. The threshold voltage VTH = VCC/2. See "Programmable-Divider Select Table" for proper decoding. TTL/CMOS Pre-Divider Select Input. Internal 25k pull-up. This two-bit input divider scales the VCO/2 frequency. See "Pre-Divider Frequency Select Table" for proper decoding. The threshold voltage VTH = VCC/2. TTL/CMOS Post-Divider Option Control. Internal 25k pull-up. Default is logic HIGH. The threshold voltage VTH = VCC/2. Logic HIGH: All LVPECL and LVDS outputs operate with their respective output frequency control (PSELx, PENx, LSEL, LEN). Logic LOW: Internal PLL is disabled, reference and XTAL signals by-passes the PLL through a /1, /4, and /16 Post-Divider. See "LVPECL and LVDS Output Post-Divider and Frequency Select Table" for proper decoding.
5
FBSEL
28 33 35 27 29 34 13, 14
PD_4 PD_2 PD_0 PD_5 PD_3 PD_1 PDSEL1, PDSEL0 DSEL
22
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SY89538L
Pin Description
Input/Output
Pin Number 3, 4 Pin Name FBIN, /FBIN Pin Function External Feedback Input used as the zero delay input. Output feeds into the inputs to configure the device in zero-delay mode, which forces the output frequency to the same frequency of the RFCK frequency. Requires external termination. See "Zero Delay FBIN Input" section for more details. Reference Clock Differential Input. Input accepts any input, single-ended or differential: TTL/CMOS, LVPECL, LVDS, HSTL, and SSTL. RFCK requires an external termination. See "Input Interface" and "Input Termination" sections for more details. Crystal Input. Directly connect a series resonant crystal across inputs. See "Quartz Crystal Oscillator Specification" table. Place crystal as close to the input as possible, keep XTAL and traces away from adjacent noisy traces to minimize noise coupling, and place the XTAL on the same side as the SY89538L (component side). 100K LVPECL Output Drivers. Terminate all LVPECL outputs with 50 to VCCO-2V. Each output pair has a respective output frequency control (PSELx, PENx, DSEL). See "LVPECL Output Post-Divider and Frequency Select Table" for proper decoding. For low-jitter applications, unused LVPECL output pairs should be terminated with pull-down resistors. See "Output Termination Recommendations" section for termination detail. Differential LVDS-Compatible Output Drivers. Output termination is 100 across the pair. For low-jitter applications, unused LVDS output pairs should be terminated with 100 across the pair. See "Output Termination Recommendations" section for details. No connect.
8, 9
RFCK, /RFCK
11, 12
XTAL2, XTAL1
17, 18 20, 21 49, 50 52, 53 38, 39 41, 42 44, 45 32, 48, 54, 61, 64
POUT0, /POUT0 POUT1, /POUT1 POUT2, /POUT2 POUT3, /POUT3 LOUT0, /LOUT0 LOUT1, /LOUT1 LOUT2, /LOUT2 NC
Input Driver Select Table
RSEL1 0 0 1 1 RSEL0 0 1 0 1 Internal Reference Clock RFCK / 8 RFCK / 4 RFCK / 2 RFCK / 1 Zero-Delay MUX Divider FBIN / 8 FBIN / 4 FBIN / 2 FBIN / 1
Table 1. Reference Input Divider and Zero-Delay MUX Divider Select Table
Pre-Divider Frequency Select Table
PDSEL1 0 0 1 1 PDSEL0 0 1 0 1 Pre-Div-Out Frequency (VCO/2) / 5 (VCO/2) / 4 (VCO/2) / 3 (VCO/2) / 2
Table 2. Pre-Divider Select Table
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Output and Frequency Select Tables
PSELx 0 0 1 1 0 0 1 1 PENx 0 1 0 1 0 1 0 1 DSEL 0 0 0 0 1 1 1 1 POUTx Disable Output (HIGH) fREF-DIV / 4 fREF-DIV / 16 fREF-DIV / 1 Disable Output (LOW) fPRE-DIV / 2 fPRE-DIV / 8 fPRE-DIV / 1
Table 3. LVPECL Output Post-Divider and Frequency Select Table LSEL 0 0 1 1 0 0 1 1 LEN 0 1 0 1 0 1 0 1 DSEL 0 0 0 0 1 1 1 1 LOUTx Disable Output (HIGH) fREF-DIV / 4 fREF-DIV / 16 fREF-DIV / 1 Disable Output (LOW) fPRE-DIV / 2 fPRE-DIV / 8 fPRE-DIV / 1
Table 4. LVDS Output Post-Divider and Frequency Select Table
Programmable-Divider Select Table
PD_5 0 0 0 0 0 ... ... 1 1 1 1 1 ... ... 1 1 1 1 1 PD_4 0 0 0 0 0 ... ... 0 0 0 0 0 ... ... 1 1 1 1 1 PD_3 1 1 1 1 1 ... ... 1 1 1 1 1 ... ... 1 1 1 1 1 PD_2 0 0 0 0 1 ... ... 0 0 0 0 1 ... ... 0 1 1 1 1 PD_1 0 0 1 1 0 ... ... 0 0 1 1 0 ... ... 1 0 0 1 1 PD_0 0 1 0 1 0 ... ... 0 1 0 1 0 ... ... 1 0 1 0 1 6-Bit Prog. Divider 8 9 10 11 12 ... ... 40 41 42 43 44 ... ... 59 60 61 62 63 fVCO fRef x 32 fRef x 36 fRef x 40 fRef x 44 fRef x 48 ... fRef fRef fRef fRef fRef ... x 160 x 164 x 168 x 172 x 176 ... ... x 236 x 240 x 244 x 248 x 252
fRef fRef fRef fRef fRef
Table 5. Programmable-Divider Select Table
Note: See "Reference Input Frequency and Valid Programmable Divider Range" section for more details.
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Absolute Maximum Ratings(1)
Supply Voltage (VCCD, VCCA, VCCO) ...... -0.5V to +4.0V Input Voltage (RFCK, FBIN)................... -0.5V to VCC XTAL Input Voltage (VXTAL1, 2) ......... VCC -1.9V to VCC Output Current (IOUT) LVPECL Outputs (Surge) .........................100mA LVPECL Outputs (Continuous)...................50mA LVDS Outputs...........................................10mA Lead Temperature (soldering, 20 sec.) .......... +260C Storage Temperature (Ts) ................. -65C to 150C
Operating Ratings(2)
Supply Voltage VCCOA and VCCOC ............................... +3.0V to +3.6V VCCOB ............................................. +2.375V to +3.6V Ambient Temperature (TA)....................... -40C to +85C Package Thermal Resistance (Junction-to-Ambient) With Die attach soldered to GND: TQFP (JA) Still-Air ......................................23C/W TQFP (JA) 200lfpm.....................................18C/W TQFP (JA) 500lfpm.....................................15C/W With Die attach NOT soldered to GND(3): TQFP (JA) Still-Air ......................................44C/W TQFP (JA) 200lfpm.....................................36C/W TQFP (JA) 500lfpm.....................................30C/W Package Thermal Resistance (Junction-to-Board) TQFP (JC) ....................................................7C/W
DC Electrical Characteristics(4)
Power Supply TA = -40C to +85C, unless otherwise stated.
Symbol VCCA VCCD VCCO ICC ICCA ICCO ICCD Parameter PLL Power Supply Control Logic Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Digital Supply Current No load, max. VCC, Note 6 Max. VCC No load, max. VCC Max. VCC Condition Note 5 Note 5 Min 3.0 3.0 2.375 3.0 Typ 3.3 3.3 2.5 3.3 240 10 55 175 Max 3.6 3.6 2.625 3.6 300 Units V V V V mA mA mA mA
LVCMOS/LVTTL Input Control Logic
VCCA = VCCD = +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VCCA and VCCD are not internally connected. They must be connected together on the PCB. 6. ICC = ICCA + ICCO + ICCD.
Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
VIN = VCC VIN = 0.5V
-125 -300
150
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Reference Clock Inputs/External Feedback Inputs
VCCA = VCCD = +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL VIN Parameter Input HIGH Voltage Input LOW Voltage Input Voltage Swing Condition RFCK, /RFCK FBIN, /FBIN RFCK, /RFCK FBIN, /FBIN RFCK, /RFCK, FBIN, /FBIN See Figure 1a. RFCK, /RFCK, FBIN, /FBIN See Figure 1b. -0.3 100 Min Typ Max VCCD + 0.3 Units V V mV
VDIFF_IN
Differential Input Voltage Swing
200
mV
100K LVPECL Output DC Electrical Characteristics
VCCA = VCCD = +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%, RL = 50 into VCCO-2V; TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing Differential Output Voltage Swing See Figure 1a. See Figure 1b. Condition Min VCCO -1.075 VCCO -1.860 550 1100 800 1600 Typ Max VCCO -0.830 VCCO -1.570 Units V V mV mV
LVDS Output DC Electrical Characteristics
VCCA = VCCD = +3.3V 10%, VCCO = +2.5V 5% or +3.3V 10%, RL = 100 across the pair; TA = -40C to +85C, unless otherwise stated.
Symbol VOUT VDIFF-OUT VOCM VOCM Parameter Output Voltage Swing Differential Output Voltage Swing Output Common Mode Voltage Change in Common Mode Voltage Condition See Figure 1a. See Figure 1b. Min 250 500 1.125 Typ 325 650 1.275 25 Max Units mV mV V mV
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AC Electrical Characteristics
VCCA = VCCD = +3.3V 10%; VCCO = +2.5V 5% or +3.3V 10%, RL (LVDS) = 100 across the output pairs, RL (LVPECL) = 50 into VCCO-2V; TA = -40C to +85C, unless otherwise stated.
Symbol fIN Parameter XTAL Input Frequency Range Reference Input Frequency Range Zero Delay Input Frequency Range Phase Detector Operating Frequency Range Output Frequency Range Internal VCO Frequency Range Output-to-Output Minimum PLL Lock Time Loop Filter Optimized for Cycle-to-Cycle Jitter * R = 50 * C1 = 0.47F * C2 = 1000pF tJITTER 1-Sigma Cycle-to-Cycle Jitter (XTAL Input) 1-Sigma Cycle-to-Cycle Jitter (RFCK Reference) Total Jitter Spur XTAL/RFCK Crosstalk-Induced Jitter BW tDC tr, tf PLL Bandwidth FOUT Duty Cycle Output Rise/Fall Time (20% to 80%) Output Rise/Fall Time (20% to 80%) Minimum SYNC Pulse Width Note 9 Note 9 Note 10 Note 11 See Table 10 14 fREF 18 LVPECL LVDS See "Synchronization" section See "Synchronization" section 4 5 80 -35 11.1 43 100 80 8 50 250 150 6 14 150 0.7 38.4 57 400 300 psRMS psRMS psPP
dBc@ fphase
fREF fOUT fVCO tSKEW tLOCK
Condition Note 7 See Table 8 See Table 9 INSEL = LOW INSEL = HIGH
Min 14 9.325 29.375 9.325 14 29.375 2352
Typ
Max 18 756 756 94.5 18 756 3024
Units MHz MHz MHz MHz MHz MHz MHz ps ms
Note 8
15
75 10
psRMS kHz % ps ps Internal clock cycle Internal clock cycle
tPW_SYNC_MIN
8
tPD_SYNC
Notes: 7. 8. 9.
Synchronization Delay
Fundamental mode, series resonant crystal. The output-to-output skew is defined as the worst-case difference between any outputs within a single device operating at the same voltage and temperature. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal.
12
10. Total jitter definition: with an ideal clock input of frequency October 2005
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Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
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SY89538L Oscillator Tips 1. Mount the crystal as close to the SY89538L as possible to minimize parasitic effects. 2. Mount the crystal on the same plane as the SY89538L to minimize on via hole inductance. 3. To minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces. 4. Keep the crystal and its traces away from adjacent noisy traces to minimize noise coupling. Figure 2 below illustrates how to interface the crystal with the SY89538L.
Functional Description
Overall Function The SY89538L integrated programmable clock synthesizer and fanout buffer with zero delay is part of a precision PLL-based clock generation family optimized for internal system clock generation (FPGAs, ASICs, NPU). Inputs XTAL The SY89538L features a fully integrated on-board oscillator, which minimizes system implementation cost. The oscillator is a series resonant, multi-vibrator type crystal driver designed to drive a 14MHz to 18MHz series resonant crystal, see Table 6 and 7 for more details on the crystal frequency range and specifications.
XTAL (MHz) Min. 14 Max. 18 X RREF 168 fVCO (GHz) Min. 2.352 Max. 3.024
Figure 2. Crystal Interface
Quartz Crystal Selection: Note: Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron
Table 6. XTAL Frequency Range and Valid Programmable Range Table Min. Frequency Range (Fundamental ModeSeries Resonant) Frequency Tolerance @ 25C Frequency Stability over 0C to 70C Operating Temperature Range Storage Temperature Range Aging (per yr/1st 3yrs) Equivalent Series Resistance (ESR) Drive Level 100 -40 -55 14 Typ. Max. 18 Units MHz
30 50
50 100 +85 +125 5 50
PPM PPM C C PPM W
RFCK The input MUX drives the PLLs phase detector, which expects a frequency between 9.325MHz and 94.5MHz. Therefore, reference clock maximum input frequency is 756MHz when the reference divider is set to a divide-by-8 and the reference clock minimum frequency is 9.325MHz when the reference divider is set to a divide-by-1. Given that the VCO frequency range is from 2.352GHz to 3.024GHz, the minimum and maximum frequency range of RFCK can be calculated as follows: Minimum Output Frequency (9.33MHz Input):
f OUT = f PHASE x Pr eDivider x FeedbackDivider Pr eDivider x PostDivider x (Div - by - 2)
f OUT =
(9.33MHz ) x (63 x 2) x (2) (5)x (8)x (2)
f OUT = 29.4 MHz
Table 7. Quartz Crystal Oscillator Specifications
Maximum Output Frequency (756MHz Input):
756 MHz x (8 x 2 ) x (2 ) 8 = (2) x (1)x (2)
f OUT
f OUT = 756 MHz
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Table 8 summarizes the input reference frequency and associated divider values:
fRFCK (MHz) Ref-Div = 1 73.5 65.3 58.8 53.5 49.0 ... 14.7 14.3 14.0 13.7 13.4 ... 9.97 9.80 9.64 9.48 9.33 Ref-Div = 8 756 672 605 550 504 ... 151 148 144 141 137 ... 103 101 99.1 97.5 96.0 X fREF 32 36 40 44 48 ... 160 164 168 172 176 ... 236 240 244 248 252 Min. 73.5 65.3 58.8 53.5 49.0 ... 14.7 14.3 14.0 13.7 13.4 ... 9.97 9.80 9.64 9.48 9.33 fREF (MHz) Max. 94.5 84.0 75.6 68.7 63.0 ... 18.9 18.4 18.0 17.6 17.2 ... 12.8 12.6 12.4 12.2 12.0 Min. 2.352 2.352 2.352 2.352 2.352 ... 2.352 2.352 2.352 2.352 2.352 ... 2.352 2.352 2.352 2.352 2.352 fVCO (GHz) Max. 3.024 3.024 3.024 3.024 3.024 ... 3.024 3.024 3.024 3.024 3.024 ... 3.024 3.024 3.024 3.024 3.024
Table 8. Reference Input Frequency and Valid Programmable Divider Range Table
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Micrel, Inc. Zero Delay FBIN Input The SY89538L features a zero delay MUX that forces the output to be at the same phase relationship as the reference. This effectively configures the SY89538L as a zero delay buffer when FBSEL is logic HIGH and the output is fed into the feedback input FBIN as shown in Figures 3a and 3b. How Does Zero Delay Work? From the block diagram,
f REF = f RFCK f FBIN and f FBK = Ref. Divider FBK Divider
SY89538L
When the PLL is locked, fREF = fFBK and since Ref. Divider = FBK Divider, fRFCK is forced to equal fFBIN. In zero delay mode, fOUT is fed into FBIN, therefore, fRFCK is forced to equal fOUT.
Figure 3a. Zero Delay Mode (LVDS Output)
Figure 3b. Zero Delay Mode (LVPECL Output)
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Ref-Divider = 1 fVCO (MHz) Min. 2.35 2.35 2.35 2.35 Max. 3.02 3.02 3.02 3.02
PostDivider PreDivider
Ref-Divider = 2 fREF (MHz) Min. 294.0 196.0 147.0 117.5 Max. 377.5 251.5 189.0 151.0
Ref-Divider = 4 fREF (MHz) Min. 147.0 98.0 73.5 58.8 Max. 188.8 125.8 94.5 75.5
Ref-Divider = 8 fREF (MHz) Min. 73.5 49.0 36.8 29.4 Max. 94.4 62.9 47.3 37.8
fOUT (MHz) Min. 588.0 392.0 294.0 235.0 Max. 755.0 503.0 378.0 302.0
fREF (MHz) Min. 588.0 392.0 294.0 235.0 Max. 755.0 503.0 378.0 302.0
1 1 1 1
2 3 4 5
2.35 2.35 2.35 2.35
3.02 3.02 3.02 3.02
2 2 2 2
2 3 4 5
294.0 196.0 147.0 118.0
378.0 252.0 189.0 151.0
294.0 196.0 147.0 118.0
378.0 252.0 189.0 151.0
147.0 98.0 73.5 59.0
189.0 126.0 94.5 75.5
73.5 49.0 36.8 29.5
94.5 63.0 47.3 37.8
36.8 24.5 18.4 14.8
47.3 31.5 23.6 18.9
2.35 2.35 2.35 2.35
3.02 3.02 3.02 3.02
8 8 8 8
2 3 4 5
73.4 49.0 36.7 29.4
94.4 62.9 47.2 37.8
73.4 49.0 36.7 29.4
94.4 62.9 47.2 37.8
36.7 24.5 18.4 14.7
47.2 31.5 23.6 18.9
18.4 12.3 Not Valid Not Valid
23.6 15.7 11.8 Not Valid
Not Valid Not Valid Not Valid Not Valid
11.8 Not Valid Not Valid Not Valid
Table 9. Zero Delay Divider Cases
Considerations when in zero delay mode: * * * The input and output frequency range is 29.375MHz to 756MHz The phase detector frequency range is 9.325MHz to 94.5MHz There are cases in which certain divider combinations at certain frequencies are not valid, see Table 9 for more details
* * *
Systematic phase offset is caused by added and parasitic capacitance Phase offset is introduced by increased trace length Phase offset second order effects can be introduced with high R die-electric constants since the velocity of electromagnetic waves slows down as the die-electric constant increases
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SY89538L
External Loop Filter Considerations
The SY89538L features an external PLL loop filter that allows the users to tailor the PLL's behavior. It is recommended that ceramic capacitors with NPO or X7R dielectric be used, since they have very low effective series resistance. For applications that require ultra-low cycle-to-cycle jitter, use the components shown in Figure 4. Larger values of the zero capacitor (capacitor shown in parallel) results in less cycle-to- cycle jitter, however the total jitter increases as the value of the zero capacitor increases. In addition, as the zero capacitor increases, loop stability decreases as the zero capacitor begins to dominate over the pole capacitor (capacitor in series with the damping resistor). The external loop filter allows the user to change the loop filter values for specific jitter requirements. Using a smaller resistor in the loop filter decreases the PLL's loop bandwidth. This results in less noise from the PLL input, but potentially more noise from the VCO. Take care to keep the loop filter components on the same side of the board and as close as possible to the SY89538L's LR and LF pins. To minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces. However, the benefit may not be significant in all applications.
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VCCA, VCCD, and all VCCO pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Figure 5.
Figure 5. Recommended Power Supply Filter
Note: For VCCA and VCCD use ferrite bead, 200mA, Murata P/N BLM21A1025. For VCCO use ferrite bead3A, 0.025 DC, Murata, P/N BLM31P005.
Figure 4. Loop Filter
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SY89538L
Synchronization
Output Synchronization Controlled by SYNC Timing Diagram
The SYNC control input is used to synchronize all divider outputs of the post divider. When a HIGH-LOW transition is applied to the SYNC control input the outputs are disabled when all post-divider outputs are LOW, see "Output Synchronization Controlled by
SYNC Timing Diagram" for details. Once SYNC is asserted with a rising edge, the outputs are enabled when all internal divider stages are reaching their LOW state. This ensures a simultaneous switching of all outputs with the next LOW-HIGH transition of the pre-divider clock.
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Micrel, Inc.
SY89538L frequencies determined by the loop filter when the SY89538L is driven by a 14MHz to 18MHz crystal when the feedback divider is effectively 168.
PLL Loop Stability
For the loop filter configurations shown in Figure 4, Table 10 below summarizes the PLL's loop stability in terms of damping factor, natural frequency, and bandwidth, and illustrates the pole and zero cutoff
Parameter Vcc RM Temperature Die Temperature VCO Frequency Charge Pump Current Loop Filter Resistor Zero Capacitor Pole Capacitor VCO Gain (KVCO) Feedback Divider Phase Detector Frequency Damping Factor Natural Frequency Ratio=Phase Detector Freq / Fc 3 -40 -18 2352 1.80E-04 50 4.70E-07 1.00E-10 3.20E+09 168 14 1.0 13600.29 513 3 -40 -18 2800 1.80E-04 50 4.70E-07 1.00E-09 4.50E+09 168 16 1.2 16127.95 417 3 -40 -18 3024 1.80E-04 50 4.70E-07 1.00E-09 4.50E+09 168 18 1.2 16127.95 469 3.3 25 55 2352 1.80E-04 50 4.70E-07 1.00E-09 2.80E+09 168 14 0.9 12721.90 586 3.3 25 55 2800 1.80E-04 50 4.70E-07 1.00E-09 3.30E+09 168 16 1.0 13811.16 568 3.3 25 55 3024 1.80E-04 50 4.70E-07 1.00E-09 3.10E+09 168 18 1.0 13386.09 681 3.6 85 125 2352 1.80E-04 50 4.70E-07 1.00E-09 2.30E+09 168 14 0.9 11530.20 714 3.6 85 125 2800 1.80E-04 50 4.70E-07 1.00E-09 1.70E+09 168 16 0.7 9912.83 1103 3.6 85 125 3024 1.80E-04 50 4.70E-07 1.00E-09 1.30E+09 168 18 0.6 8668.52 1623
Units V C C MHz A Ohms F F Hz/V Integer MHz
Hz
Table 10. PLL Loop Stability
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Micrel, Inc. Figure 6 shows the open and closed loop gain of the SY89538L. The closed loop-gain plot shows that the SY89538L when configured with the recommended loop filter values has essentially no jitter peaking near the -3dB point. In addition, the open loop curve shows the frequency at which unity gain occurs for a typical case of the SY89538L with VCC = 3.3V at TA = 25C. At unity gain, Figure 7 can be used to determine the phase margin or stability of the SY89538L.
SY89538L
Figure 8. Loop Filter Control Voltage vs. Frequency at 3.3V, TA = 25C
dB
Frequency (Hz)
Figure 6. Open and Closed Loop Gain at VCC = 3.3V, TA = 25C
Figure 9. Frequency vs. Loop Filter Control Voltage at 3.3V, TA = 25C
Phase Margin ()
Input Interface
RFCK and FBIN are designed to accept any differential or single-ended input signal 300mV above VCC or 300mV below GND. RFCK and FBIN should not be left floating. Tie either the true or complement input to GND, but not both. A logic zero is achieved by connecting the complement input to GND with the true input floating. For TTL input, tie a 2.5k resistor between the complement input and GND. LVDS, CML and HSTL differential signals may be connected directly to the reference inputs.
Frequency (Hz)
Figure 7. Phase Margin Plot at VCC = 3.3V, TA = 25C
Figure 8 illustrates the VCO frequency versus the loop filter control voltage at 3.3V, TA = 25C. The normal loop filter control voltage is -300mV to +300mV. Figure 9 illustrates the VCO gain curve at VCC = 3.3V, TA = 25C. With this set of information, determining the loop stability with other sets of loop filter configurations is possible.
Figure 10. Simplified Input Structure
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SY89538L
Input Termination (RFCK and FBIN)
Figure 11a. LVPECL Interface (DC-Coupled)
Figure 11b. LVPECL Interface (AC-Coupled)
Figure 11c. CML Interface (DC-Coupled)
Figure 11d. CML Interface (AC-Coupled)
Figure 11e. LVDS (DC-Coupled)
Figure 11f. 2.5V LVPECL (DC-Coupled)
Figure 11g. 2.5V CML (DC-Coupled)
Figure 11h. Single-Ended Input Interface
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SY89538L The LVPECL output can also be terminated with three 50 resistors as shown in Figure 12b. A 0.1F low ESR decoupling capacitor from VCC to Y-Junction is recommended in order to reduce noise in the signal. AC-Coupled LVPECL Termination While terminating an AC-coupled LVPECL signal, pulldown resistor is used to create a DC current path to GND to produce an output swing. For 3.3V supply, 100 provides the necessary pull-down. At the final destination, proper termination to create a VCC-1.3V termination bias is required 82||130. Please refer to Figure 12c.
Output Bank and Frequency Control
There are five independently programmable output frequency banks, four differential LVPECL output banks and one differential LVDS output bank with three output pairs. Each bank has frequency control DSEL, SELx and Enx to generate different divider ratios (see "LVPECL and LVDS Output Post-Divider Frequency Select" Tables). It can be programmed for pass-through, internal divided VCO clock divide-by/2, /8 or disable state. When disabled, the noninverted output goes to static LOW and the inverted output goes to static HIGH. Output Logic Characteristics See "Output Termination Recommendations" for proper termination. When LVPECL single-ended output is desired, the unused complimentary output should be terminated. Unused LVPECL output pairs can be left floating. LVDS output pairs should be terminated with 100 across the pair. In order to minimize jitter and skew, unused LVDS output banks and unused LVDS output pairs should be terminated with 100 across each pair. LVPECL Outputs: * Typical voltage swing is 800mV into 50. * Common mode voltage is VCCO-1.3V. LVDS Outputs: * Typical voltage swing is 325mV into 100. * Common mode voltage is 1.2V.
Figure 12a. LVPECL Parallel Thevenin-Equivalent
Output Termination Recommendations
LVPECL LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing which results in low EMI. LVPECL is ideal for driving 50-and-100-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Single-ended termination, Parallel Termination Thevenin-Equivalent, 3-Resistor Y-Termination, and AC-coupled termination. Single-Ended LVPECL Termination Unused output pairs may be left floating. Terminating single-ended and unused outputs will enhance the performance. Terminate LVPECL outputs by 50 to VCC-2V. The unused input terminal must be biased to VCC-1.3V using a resistor network. See Figure 11h for more details. DC-Coupled LVPECL Parallel Termination Terminate LVPECL by an output impedance of 50 to VCC-2V. Termination resistor values are a function of VCC. For a 3.3V supply, the optimal parallel combination is 130||82. See Figure 12a for details.
Figure 12b. LVPECL Parallel Termination
Figure 12c. LVPECL AC-Coupled Parallel Thevenin-Equivalent
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Micrel, Inc. LVDS LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a
SY89538L function of LVDS input, is kept to a minimum, to keep EMI low conveniently to ASKs and FPGAs. Each LVDS output pair requires 100 across the differential pair at the end destination (often intended integrated into the ASIC).
Related Product and Support Documentation
Part Number SY89537L Function 3.3V, Precision LVPECL and LVDS Programmable, Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay New Products and Applications MLF
TM
Data Sheet Link http://www.micrel.com/product-info/products/sy89537l.shtml
HBW Solutions
www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf
Application Note
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SY89538L
Package Information
64-Pin EPAD-TQFP (H64-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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